1. FIeld Of The Invention
This invention is directed to a method of forming a silicon-on-insulator structure and more particularly to the formation of such a structure using a novel etch stop comprising a silicon-germanium alloy.
2. Background Description
In the present era of very large scale integration (VLSI), in which the dimensions of transistors and other semiconductor structures are shrinking below one micrometer, a host of new problems must be addressed. In general, greater isolation is required between devices. For CMOS applications, this isolation must prevent latch-up. At the same time, this increased isolation must not be provided at the expense of available chip space.
Silicon-on-insulator (SOI) technology appears to be a particularly promising method of addressing this problem. Silicon-on-insulator substrates are in use for the fabrication of devices that are high speed, resistant to latch up, and are radiation hard.
Separation by Implanted oxygen (SIMOX) has been the most thoroughly studied SOI system to date to replace silicon on sapphire. A general example of this technology is shown in the article by R. J. Lineback, "Buried Oxide Marks Route to SOI Chips", Electronics Week, Oct, 1, 1984, pp. 11-12. As shown in this article, oxygen ions are implanted into a bulk silicon to form a buried oxide layer therein. The implant is then annealed for two hours so that portion of the silicon lying above the buried oxide is single-crystal silicon. The various semiconductor devices are then formed on the single-crystal layer. The underlying buried oxide provides isolation between adjacent devices and the substrate region.
Although SIMOX is a promising technology, threading dislocations generated by the implantation in the active device region limit the performance of the material. In addition, the buried oxide is of poor quality resulting in back channel leakage.
Bond and etch back silicon-on-insulator (BESOI) technology, as an alternative to SIMOX, has the advantage of a cleaner oxide/silicon interface with less defects and charge trapping states at the buried oxide. This material is generated by oxidizing the seed and/or handle wafers, followed by bonding the two wafers. The active device region is generated on the seed wafer by lapping and etching to the desired film thickness. Although this technology is suitable for the fabrication of 600 nm SOI, the presence of an etch stop is essential to achieve SOI wafers with a nominal thickness of 500 nm or less.
Heavily doped boron regions placed by diffusion or implantation into the silicon have been reported to make an effective etch stop, and CMOS devices fabricated from these materials have been reported. Silicon membrane technology uses similar techniques to fabricate these materials. The limitations inherent in the utilization of boron is that boron is a p-type dopant in silicon. Both implantation and diffusion of boron results in residual p doping of the silicon film. Also, boron incorporated by ion implantation and annealing results in the generation of threading dislocations in the device region. This limits performance of devices made from these materials.